In large data base systems where many work units or subtasks have a need to share access to the same records, there is a need to manage concurrent access to maintain integrity of the data.
One prior art approach to data sharing is illustrated by the concurrent accessing of a VSAM (Virtual Sequential Access Method) data set by two or more subtasks within a single partition, by two or more job steps (partitions), and by any number of users (cross-system sharing). As is explained in VSAM Primer and Reference, IBM Publication G320-5774-01 (1979), at pages 95-97, various options are available for opening a data set for either read or write.
In VSAM cross-partition/region sharing the option is defined by the SHARE OPTIONS parameter of the DEFINE command when the VSAM data set is defined. By a first option, a data set may be opened by only one user for output processing (to update or add records), or by multiple users for read operations only. By this option, full read and write integrity is provided. In a second option, a data set can be opened by one user for output processing and by multiple users for read-only processing. In this option, write integrity is provided, but read integrity is not, as users can read a record that is in the process of being updated. In a third option, a data set can be opened by any number of users for both read and write operations, and no integrity (read or write) is provided by VSAM.
In VSAM cross-systems sharing, by a first option, a data set can be opened by any number of users for both read and write operation, and no integrity is provided by VSAM. In a second option, a data set can be opened by any number of users for both read and write operations--however, VSAM provides a new buffer for each direct processing request, and RESERVE and RELEASE macros must be issued by users to maintain data set integrity.
In each of the above options, except the first, the user of VSAM must maintain data set integrity, issuing the required ENQ/DEQ or RESERVE/RELEASE macros.
In the prior art IBM IMS/VS product, the issuance of such macros is a function of the Program Isolation facility. (See IMS/VS Version 1 Primer, Program Number 5740-XX2, IBM Publication SH 20-9145-0, pages 3.12-3.14, G320-5771-02, pages 41-46, and S320-5767-01, pages 3.12-3.13; and IMS/VS Version 1 Recovery/Restart, IBM Publication GG24-1515-00, pages 6.1-6.4, B.1-B.21.) However, this facility does not provide for multiple concurrent access to common data by users executing on different central electronic complexes (CEC's), resulting in a significant impediment to the efficient use of data bases by large organizations.
One prior art approach to enabling multiple concurrent access to common data is S. B. Behman, et al, U.S. patent application Ser. No. 280,648, filed July 6, 1981, a continuation of U.S. patent application Ser No. 965,810, filed Dec. 4, 1978 (abandoned), for External Enqueue Facility for Access to Sharable Data Facilities. Behman, et al, is a concurrency notification facility. External Enqueue Facility (EEF) 5 maintains for each member CPU and congruence class an interest bit. When set, the interest bit indicates that the CPU holds or is waiting for a lock on a data resource of the corresponding concurrence class. Each CPU includes an Internal Enqueue Facility (IEF), which maintains for each congruence class a lock bit. Request for access to data resource is granted by the CPU if the corresponding lock bit in the IEF is set; but if not set, the request must be communicated first to the EEF and thence to other CPU's showing in the EEF an interest in the congruence class of the request. The Behman system is, in effect, a concurrency notifier, there being no structure described for controlling concurrent access. Furthermore, the EEF structure is implemented either in a separate hardware device or in one of the CPU's. A failure in the EEF effectively prevents communication between the CPU's and processing of any data resource access request by any of the CPU's: there being no provision in each CPU for maintaining locks held by failed CPU's or the EEF for subsequent recovery.